1. Field of the Invention The present invention relates to a pipeline type analog to digital converter including plural series connected analog to digital converter stages.
2. Description of the Background Art
FIG. 46 indicates the construction of a conventional pipeline type A/D converter. The A/D converter shown in this drawing is one which was disclosed in "IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE, P.P.26.4.1 .about.26.4.4, STEPHEN H. LEWIS ET AL". Each stage is composed of a 2-bit A/D conversion sub-block ADSC, a D/A converter DAC for converting the result of A/D conversion to an analog value, a subtracting circuit .SIGMA. and a sampling & holding amplifier SHA having a degree of amplification to double value, and this converter generates 10 bits of digital output values in total by taking a 9-stage construction.
In the pipeline type A/D converter indicated in FIG. 46, the subtracting circuit .SIGMA. and the double amplifier SHA must be of high accuracy among the constituting elements of the respective stages.
Here, the description will be given on the operating principle of this type of A/D converter. FIG. 47 indicates the operating principle.
In this drawing, the A/D converter in the first stage roughly performs A/D conversion in 2 bits. In this case, the value of input voltage Vin is, in its relation with voltages Vr1, Vr2, Vr3 of intermediate taps obtained by resistively dividing the voltage between the upper limit value VRT of reference voltage and the lower limit value VRB of reference voltage., larger than the tap voltage Vr2 but smaller than the tap voltage Vr3. Therefore, the result of A/D conversion in the first stage becomes code "10".
Here, if the electric potential difference (Vin-Vr2), defined as .DELTA.V, can be multiplied by 4 accurately, the A/D converter in the next stage can share the input voltage range determined by the reference voltage VRT and the reference voltage VRB in the first stage as its input voltage range VRT2 to VRB2, and therefore, the voltage 4.multidot..DELTA.V obtained by multiplying the voltage .DELTA.V with 4 is larger than the lower limit value VRB2 of the reference voltage in the second stage but smaller than the tap voltage Vr1. Consequently, the result of A/D conversion in the second stage becomes code "00".
Moreover, if the electric potential difference (4.multidot..DELTA.V-VRB2) between the voltage 4.multidot..DELTA.V obtained by multiplying the voltage .DELTA.V with 4 and the lower limit value VRB2 of the reference voltage in the second stage can be further multiplied by 4 accurately, the A/D converter in the further next stage can also share the input voltage range VRT to VRB in the first stage as its input voltage range VRT3 to VRB3, and, as a result, the voltage (4.multidot.4.multidot..DELTA.V) obtained by multiplying the voltage (4.multidot..DELTA.V) with 4 becomes larger than the tap voltage Vr2 but smaller than the tap voltage Vr3. Therefore, the result of A/D conversion in the third stage becomes code "10". In the same way, the output codes in the respective stages are determined one after another.
As a result, the analog input voltage Vin in the case of FIG. 47 can be obtained by adding sequentially from the output of the A/D converter in the first stage to the output of the A/D converter in the final stage, taking account of their weights. Namely, a digital code reading as 100010 . . . is output, so that the digital code corresponding to the analog input voltage Vin is determined.
On the other hand, FIG. 48 indicates the construction of another conventional 10-bit A/D converter disclosed in "IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE, P.P.16.7.1.about.16.7.4, MICHIO YOTSUYANAGI ET AL". This A/D converter is a pipeline type A/D converter of 3-stage construction, each stage consisting of a 4-bit A/D converter block. The S/H circuit and the subtracting block in each stage are designed for sampling an inputted analog value and holding the sampled value for a certain period of time to perform the A/D conversion, D/A conversion and subtraction during that period.
(First Problem of the Conventional Arts)
Conventional A/D converters are constructed as described above. Therefore, in the case stated in FIG. 47, it is necessary to amplify the difference between the analog input voltage and the reference voltage or the intermediate tap voltage accurately to 4.00 times the initial value and the linearity of the A/D converter is lost in case of poor accuracy of this amplification degree.
Therefore, in the prior arts, it is necessary to realize the sampling & holding amplifier as a high-accuracy amplifier. For that reason, the method conventionally practiced for realizing high-accuracy amplification to 4.00 times the initial value, etc. consists in giving feedback to a high-speed amplifier of sufficiently large amplification degree (ideally with gain .infin., realistically with gain of at least magnification 1000) to realize the high-accuracy amplifier and set the amplification degree exactly to 4.00 times.
However, a large amount of electric power must be consumed to actually realize such high-speed amplifier of large amplification degree in the predetermined precision. This presents a problem of large electric power consumption in both the S/H circuit SHA provided in the input portion of the A/D converter and the sampling & holding amplifier on output side in each stage of FIG. 46.
In the same way, also in the case of the A/D converter in FIG. 48, high-speed amplifiers of large amplification degree operated with feedback are utilized in the S/H circuit and the subtractor. For that reason, the same problem of increased electric power consumption is produced also with the A/D converter of FIG. 48.
(Second Problem of the Conventional Arts)
In a conventional pipeline type A/D converter, the analog input signal is first applied to the S/H circuit, as it is also indicated in both FIG. 46 and FIG. 48. Therefore, in the case where the S/H circuit is provided in the first stage this way, the S/H circuit concerned is requested to have an accuracy of the range of a size equal to the dynamic range of the input signal. For example, when the voltage range of the analog input signal is 1 Vpp, the S/H circuit which receives such analog input signal must have the accuracy over the range of 1 V and its linearity must be controlled to no more than 0.5 mV when constituting a 10-bit A/D converter.
However, it is practically difficult to construct a S/H circuit having such sufficient linearity over such a wide input range and, for that reason, a S/H circuit as described above is usually realized by applying feedback to a high-speed amplifier with high gain.
Therefore, (with conventional pipeline type A/D converter), there was a problem that the electric power consumption in the S/H circuit which receives the analog input signal gets larger, increasing the electric power consumption of the entire A/D converter.